Method and system for creating a netlist allowing current measurement through a sub-circuit

ABSTRACT

A system and method for manipulating a netlist, at the time that the netlist is being created, to permit measurement of current flow through a net, or combination of nets, of a sub-circuit during a subsequent simulation process, the manipulation of the netlist including identifying nets through which current flow is to be measured, creating “artificial” nets for the identified nets, substituting the “artificial” nets for the identified nets in the netlist file, and connecting a power supply between the artificial net and the identified net for which it has been substituted.

[0001] A portion of the disclosure of this patent document containsmaterial which is subject to copyright protection. The copyright ownerhas no objection to the facsimile reproduction by anyone of the patentdocument or the patent disclosure, as it appears in the Patent andTrademark Office patent files or records, but otherwise reserves allcopyrights whatsoever.

FIELD OF THE INVENTION

[0002] The present invention relates to integrated circuits and inparticular to the design, testing, and verification of integratedcircuits.

BACKGROUND

[0003] Today's integrated circuits (ICs) may contain many circuitelements. Computer-aided design (CAD) and computer-aided engineering(CAE) tools are essential in producing these complicated integratedcircuits. Circuit design can be represented by a schematic. Schematicsconsist of symbols instances connected by nets which demonstrate thefunctional design of the circuit. Symbol instances are pictorial iconsthat represent a complete functional block Symbol instances can beprimitive elements, such as transistors and resistors. Symbol instancescan also be abstractions of combinations of primitive elements, such asNAND gates and NOR gates. Symbol instances can also be higher levelgroupings of these various elements.

[0004] To produce the complicated schematics of an integrated circuit,CAD software can be used. CAD software allows symbols to be saved insoftware libraries for use by all circuit designers within the entireIC. Portions of the IC can be easily replicated, deleted, and changedwith the CAD software, forming a plurality of sub-circuits.

[0005] Another representation of a circuit design is the netlist. Anetlist is a text file describing a circuit. The netlist lists all ofthe symbol instances and their connecting nets within a schematic. CAEsoftware can be used to translate a schematic into a netlist. In a flatnetlist, all of the higher levels of symbol instances are replaced bytheir primitive components. Thus, a schematic having multiple instancesof NAND gates would result in a netlist having a collection oftransistors.

[0006] A netlist is used as input to another CAE tool, the simulator.Simulators use netlists and input stimulus files to imitate the functionof the circuit design without having to incorporate the design inhardware. Simulating a circuit by providing netlists and stimulus datais an efficient and cost worthy method of testing a circuit design todetermine how the circuit performs prior to fabrication of the circuitas an integrated circuit structure. Circuit performance is determined bya function commonly referred to a probing, whereby currents and voltagesare monitored at various points in the circuit design.

[0007] Processes have been proposed in the prior art for measuringcurrent and/or voltages internally of sub-circuits of the circuitdesign. For example, META software available from Cadence DesignSystems, Inc., San Jose, Calif., provides a way to measure current byadding a device for each node and then using arithmetic to add up all ofthe currents. Also, a simulator program, commercially available fromADM, provides a method for measuring current through a sub-circuit in ahierarchical netlist. However, neither one of these arrangements allowsfor the measurement of current in sub-circuits of a schematic throughthe application of a supply to the sub-circuits on a global basis fordirectly measuring current in sub-circuitsduring testing andverification of the circuit being designed.

SUMMARY OF THE INVENTION

[0008] The present invention provides a method and system for allowingthe measurement of current in a sub-circuit of a schematic duringsimulation testing. The current measurement function is provided throughthe manipulation of a netlist of the schematic, as the netlist is beingcreated, by interpreting instance properties to identify nets throughwhich current flow is to be measured. “Artificial” nets are created andsubstituted for the nets specified by the instance properties, allowingthe connection of a power source to specified nets of the instance.

[0009] In accordance with the invention, for each instance that includesa net, or combination of nets, through which current flow is to bemeasured, a property is assigned to the instance on the schematic, theproperty identifying the net and the power supply to be connected to thenet. A flat netlister formatter provided by the invention is interfacedwith a conventional flat netlisting engine, whereby, as the flatnetlisting engine creates a flat netlist from the schematic, proceduresof the flat netlister formatter interpret each property, replace eachnet identified by the property with an artificial net, and declare thepower supply to be connected between the artificial net and the netoriginally called out, to allow current flow through the net to bemeasured during a subsequent simulation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a top schematic including an instance “load” and aninstance of a NAND gate;

[0011]FIG. 2 is a lower-level schematic of the instance “load” of FIG.1;

[0012]FIG. 3A is a bottom schematic of the instance “load” and NAND gateof FIG. 1;

[0013]FIG. 3B is a bottom schematic similar to that of FIG. 3A andshowing artificial nets substituted for the power supply net vcc! inaccordance with the invention;

[0014]FIGS. 4A and 4B are a flat netlist created by a flat netlisterprogram and the present invention, the measure current net engine,corresponding to the bottom schematic of FIG. 3A including artificialnets;

[0015]FIG. 5 is a block diagram of a computer system for creatingschematic designs and for building flat netlists;

[0016]FIG. 6 is a block diagram showing a conventional flat netlistertraversal engine and the flat netlist formatter provided by theinvention;

[0017]FIG. 7 is a flow chart illustrating the steps taken by the flatnetlisting driver and the flat netlist formatter in the creation of aflat netlist that is adapted to permit measurement of current through anet of an instance; and

[0018]FIGS. 8A and 8B are an exemplary listing of code for creatingartificial nets in the procedure of FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0019] In the following description, reference is made to theaccompanying drawings which form a part hereof and in which is shown byway of illustration a specific embodiment in which the invention may bepracticed. This embodiment is described in sufficient detail to enablethose skilled in the art to practice and to use the invention, and it isto be understood that other embodiments may be utilized and that changesmay be made without departing from the spirit and scope of the presentinvention. The following description is, therefore, not to be taken in alimiting sense and the scope of the invention is defined by the appendedclaims. In the figures, elements having the same number performessentially the same functions.

[0020] Schematic

[0021] The invention is described with reference to an application to asub-circuit or cell of a schematic 102 in FIG. 1. The sub-circuitincludes an instance I1 of a circuit called “load” and an instance GNA0of a NAND gate. Such schematic 102 can be created by a computer-aidedengineering (CAE) tool or schematic design tool. One such CAE tool isDesign Entry available from Cadence Design Systems, Inc., San Jose,Calif.

[0022] The sub-circuit has an input node or net 103 labeled “A” and anoutput node or net 104 labeled “OUT”.The Instance I1 includes an inputnet 105 which is connected to input net 103, an output net 106, andoutput net 107. Instance GNA0 includes input nets 108 and 109 which areconnected to nets 106 and 107, respectively, and an output net 110 whichis connected to output net 104.

[0023] Instances I1 and GNA0 also have a net 112, which is labeled vcc!and a net 113, which is labeled gnd!, by which the power supply isprovided to the instances. Conventionally, the power supply is carriedthroughout the circuit diagramed by the schematic 102 by global netswhich are customarily denoted as vcc! and gnd!. The “!” character in thenet name indicates that the net is global to the entire schematic.

[0024]FIG. 2 is the next lower level representation of instance I1 ofschematic 102. In FIG. 2, instance I1 is revealed to include twoparallel circuit paths 201 and 202, each of the circuit paths includingan inverter, a resistor and a capacitor. Thus, circuit path 201 includesa first instance GI0 of an inverter 204, a resistor R2 and a capacitorC1. Instance GI0 of the inverter has an input connected to input net 105and an output 206 that is labeled I1/net 14. Resistor R2 is connectedbetween the output 206 and the output net 107. Capacitor C1 is connectedbetween the output net 107 and ground. Circuit path 202 includes asecond instance GI1 of inverter 204, a resistor R3 and a capacitor C0.Instance GI1 of the inverter has an input connected to input net 105 andan output 208 that is labeled I1/net 6. Resistor R3 is connected betweenoutput 208 and the output net 106. Capacitor C1 is connected between theoutput net 106 and ground.

[0025] The present invention allows “artificial” nets or ports to becreated in specific sub-circuits of a schematic, such as schematic 102.In accordance with the present invention, the creation of such“artificial” nets or ports is accomplished by the use of “propertylists”. Property lists are data structures supported by Design Entry andother CAD software systems. A property list for an instance symbol ornet consists of a property name and a value to be associated with theproperty name. In the exemplary embodiment, each of the instances GI0and GI1 of inverter 204 has a property “MeasI” which is indicated at theinstance. In the example, the property MeasI of these instances has aproperty value of “inv0 vcc!” for instance GI0 and a property value of“inv1 vcc!” for instance GI1. The present invention achieves thecreation of local artificial nets through the creation of this “MeasI”Property list. In the exemplary embodiment, the artificial nets allowmeasuring of current flow within the instances GI0 and GI1, by causing a“local” power supply to be inserted between the existing power supplyinputs as will be described. However, the property MeasI allows thecircuit designer to specify which nodes or nets of the instance throughwhich current flow is to be measured, and the nets that can be specifiedby this property are not limited supply nets such as nets 112 and 113 towhich are applied vcc! and gnd!, but can be other nets of the instance.Also, the property MeasI can indicate a plurality of nets through whichcurrent flow is to be measured. For example, the property MeasI can havea property value of “inv0 vcc! gnd! 206, in which case current flow willbe measured through the net 112 which is connected to vcc!, the net 113which is connected to gnd!, and the net 206 (which is assigned the netname 1/net 14 by a flat netlisting traversal engine) between the outputof instance GI0 of the inverter and resistor R2.

[0026] The MeasI property list allows mapping of the nets of schematics,such as schematic 102. This property list allows the circuit designer tomap a global net, such as vcc!, to a local artificial net that iscontained within a block of the schematic 102. In the exemplaryembodiment, the MeasI property list states that in instance GI0, theglobal net vcc! is mapped to a local artificial net “inv0 vcc!”, and ininstance GI1, the global net vcc! is mapped to a local artificial net“inv1 vcc!”. Such mappings indicate that whenever the global net vcc! isreferenced within an instance, a “local” power supply should beconnected into the circuit.

[0027] A new, or “artificial” net (identified as “supply_net”) iscreated in the netlist for each of the nets in the MeasI property. Inthe exemplary embodiment, two “artificial” nets are created in thenetlist, and these nets are identified as “inv1_1” and “inv0_1”. Net“inv1_1” is located in the instance GI1 of the inverter 204 as indicatedby string portion “inv1”, which is the supply name. The net throughwhich current is to be measured through, is a net to which vcc! isapplied as indicated by string portion “_1”. As will be shown, the“vcc!” net 112 is given thenet number “1” in a flat netlist that iscreated from the schematic 102. During the creation of the flat netlist,these “artificial” nets are swapped, or substituted for the nets calledout. These new “artificial” nets are global to the netlist. To completethe task of manipulating the netlist to allow current flow through the“vcc!” to bemeasured, a voltage source is inserted between the new netand the original net in the last step of the procedure when artificialnets have been substituted for nets called out.

[0028] Referring now to FIG. 3A, there is illustrated a bottom levelschematic of schematic 102. In FIG. 3A, the two instances GI0 and GI1 ofthe inverter 204 are shown as their elementary pair of p-type and n-typetransistors. For example, instance GI1 includes n-channel transistor M4and p-channel transistor M5. Similarly, instance GI0 includes n-channeltransistor M6 and p-channel transistor M7.

[0029] Also in FIG. 3A, a bottom level schematic of the instance GNA0 ofthe NAND gate is provided. Instance GNA0 includes p-channel transistorsM8 and M9 and n-channel transistors M10 and M11. The NAND gate isconventional and accordingly is not described in detail. The gates of M8and M10 are commonly connected to net 106. The gates of M9 and M11 arecommonly connected to net 107. The sources of M8 and M9 are connected tovcc! The drains of M8 and M9 are commonly connected to net 104. Thejunction of the drain of M10 and the source of M11 define a net 24.

[0030] Note that in FIG. 3A, the power supply is finally integrated as apart of schematic 102. In FIG. 3A, the power supply vcc! is routed tothe transistor pairs of the two instances GI0 and GI1. In a traditionalschematic, the power supply would be available through the global netvcc!. The present invention, however, allows an artificial local net tobe substituted for the global vcc! net. Referring to FIG. 3B, ininstance GI0, the local artificial net inv0_1 is substituted for net 1(vcc!). Similarly, in instance GI1, the local artificial net inv1_1 issubstituted for net 1 (vcc!). This substitution is accomplished throughthe entry of the MeasI property list at the higher level of schematic102 in the sub-circuit “load” shown in FIG. 2, to identify each net ineach instance through which current is to be measured.

[0031] To be useful to a simulator software package, schematic 102, mustbe translated into a textual file. This translation is done by atranslation program, called a netlister. There are two types ofnetlisters. A flat netlister traversal engine creates a netlist showingthe primitive elements of schematic 102. The netlist of FIGS. 4A and 4Bare a flat netlist 402. A hierarchical netlist includes definitions ofhigher level blocks of schematic 102, such as the definition of instanceI1, and/or GNA0 in FIG. 1. In one embodiment, the netlister used toproduce a flat netlist is the tool Flat Netlister (FNL). The skeletonprogram of the FNL flat netlisting tool is provided by Cadence DesignSystems, Inc., San Jose, Calif. as part of their “Open SimulationSystem” environment. Other netlisters can be used. The FNL flatnetlisting tool available from Cadence Design Systems, Inc., allows theeasy integration of client-written subroutines to perform outputformatting. In one embodiment of the invention, the process formanipulating the netlist to permit current measurement through-nets ofinstances of a schematic during simulation, is implemented as a set ofthese interfaced subroutines to the FNL flat netlisting tool.

[0032] Flat Netlist

[0033] The flat netlist 402 of FIGS. 4A and 4B is a representation ofthe instances and nets necessary to describe the schematic 102 to theHSPICE simulator. In the exemplary embodiment, the flat netlist 402 isproduced from the schematic using the skeleton program of the FNL flatnetlisting tool. However, other netlisters could be used.

[0034] The netlist is a textual coded description of all primitiveelements in schematic 102 and how these elements are connected by nets.The flat netlist 402 describes the instances and nets specified in adesign in a format that is useable by a simulator. In schematic 102,instances and nets can be referenced with string names or not referencedat all. The FNL flat netlisting tool, however, assigns each instance andnet a distinct reference number.

[0035] Each line of the flat netlist 402 in FIGS. 4A and 4B has a numberfrom 1 to 65 preceded by “4.”, for correspondence to FIGS. 4A and 4B.The following description is correlated with the line numbers for eachline in FIGS. 4A and 4B. In this embodiment of a netlist, all commentsbegin with an asterisk (*)

[0036] In FIGS. 4A and 4B, the global net vcc! is assigned net number 1,or net 1. This fact is noted in the comment line at line 4.7. Similarly,the global net gnd!, or ground, is assigned net number 0 as noted inline 4.8. In addition, the nets 106 and 107 of the circuit “load” whichcorrespond to net4 and net5, respectively, are mapped to net 6 and net 7as noted in lines 4.11 and 4.12. Also, as noted in lines 4.15 and 4.16,certain nets in instance I1 (circuit “load”) are mapped as net 9, whichcorresponds to I1/net 14, and as net 10, which corresponds to I1/net6.

[0037] The instances of the resistors and capacitors in the circuit“load” (FIG. 2) are described in lines 4.18 to 4.26. Lines 4.20 and 4.22declare capacitors C0 and C1 of schematic 102. Capacitor definitions arenoted with the initial letter “C”.In line 4.20, capacitor C0 is said tobe connected between net 6 (net4 in FIG. 2) and net 0 (ground) and tohave a value of 1e-12, or 1 picofarad. In line 4.22, capacitor C1 issaid to be connected between net 7 (net5) and net 0 (ground) and to havea value of 4e-12, or 4 picofarads.

[0038] The resistor R2 is declared in line 4.24 as being connectedbetween net 10 (I1/net6) and net 6 (net4) and having a value of “1e3” or1000 ohms. Resistor R3 is declared in line 4.26 as being connectedbetween net 9 (I1/net 14) and net 7 (net5) and having a value of 500ohms.

[0039] Lines 4.28 to 4.37 define the transistors I1/GI1/MNA andI1/GI1/MPA of instance GI1. For example, line 4.31 states thattransistor I1/GI1/MNA, identified as M4 in line 4.31, is of an n-typemosfet, having its drain connected to net 10 (I1/net6 in FIG. 3A), itsgate connected to net 5 (net6 in FIG. 3A), its source connected to net 0(gnd!), and its substrate connected to net 3 (vbb!). In a conventionalnetlist, the instance of transistor I1/GI1/MPA would be declared asstated in line 4.34, which is indicated as a comment line. That is, theinstance, identified as M5 in line 4.34, is of a p-type mosfet, havingits drain connected to net 10 (I1/net 6 in FIG. 3A), and its gateconnected to net 5 (net6 in FIG. 3A). A conventional netlist would statethat the source of the transistor M5 is connected to net 1 (vcc!), andthe substrate of the transistor M5 is connected to net 1 (vcc!), in themanner stated in comment line 4.34.

[0040] Transistors I1/GI0/MNA and I1/GI0/MPA of instance GI0 are definedin a similar manner in lines 4.39 to 4.48. Again, a conventionalnetlist, would declare the source of the transistor M7 being isconnected to net 1 (vcc!), and the substrate being connected to net 1(vcc!) as stated in comment line 4.45.

[0041] Digressing, in accordance with the invention, the flat netlist402 of FIGS. 4A and 4B includes the “artificial” local nets inv1_1 inline 4.37 and inv0_1 in line 4.48 that are supported by the presentinvention and are illustrated in FIG. 3B. Lines 4.33 to 4.36 have beenadded to the netlist by the present invention as comment lines toindicate that the MeasI property on instance GI1 causes all vcc! nets tobe changed to inv1_1. Similarly, lines 4.44 to 4.47 have been added bythe present invention as comment lines to indicate that the MeasIproperty on instance GI0 causes all vcc! nets to be changed to inv0_1.

[0042] Thus, in line 37, which describes the p-type mosfet in instanceGI1, the two occurrences of vcc! (net 1) have been replaced by theartificial net inv1_1. Also, in line 48, which describes the p-typemosfet in instance GI0, the two instances of vcc! (net 1) have beenreplaced by the artificial net inv0_1.

[0043] Continuing with the description of the netlist 402, lines 4.53 to4.61 declare the p-channel transistors GNA0/MPB, GNA0/MPA, and then-channel transistors GNA0/MNB and GNA0/MNA of instance GNA0 of the NANDgate. For example, line 4.55 declares, in the conventional manner, thattransistor GNA0/MPB, identified as M8 in line 4.55 (and in FIG. 3A), isa p-type mosfet, having its drain connected to net 4 (output 104), itsgate connected to net 6 (net 106 in FIG. 3A), its source connected tonet 1 (vcc!), and its substrate connected to net 1 (vcc!), as indicatedby the series of numbers “4 6 1 1” that follow the designation M7.Transistors M9 (GNA0/MPA), M10 (GNA0/MPB) and M11 (GNA0/MNA) are definedin a similar manner in respective lines 4.57, 4.59 and 4.61, withtransistors M10 and M11 being n-channel transistors.

[0044] In accordance with the invention, voltage sources 215 have beendeclared in lines 4.64 and 4.65. For example, line 4.64 declares that asupply “vinv0_1” is connected between the artificial net “inv0_1” andthe net having the net number “1” ( vcc!). The supply is said to provide0 volts as-represented by the number “0”. Similarly, line 4.65 declaresa supply “vinv1_1” connected between the artificial net “inv1_1” and net1 (vcc!). The supply provides 0 volts as represented by the number “0”in line 4.65. Referring to FIG. 3B, the connection of the voltagesources 215 (which correspond to “vinv1_1” and “vinv0_1”) between vcc!and the source of the transistor M5, and between vcc! and the source ofthe transistor M7, are represented by the dashed lines.

[0045] Computer System

[0046]FIG. 5 is a block diagram of a computer system 500 in which thepresent invention is capable of being executed. The computer systemincludes input devices 505, such as a keyboard, mouse or digital drawingpad, a display unit with a screen 510, a printer or plotter 515, storagedevices 520, and a processing unit 525. Computer system 505 can be a Sunworkstation available from Sun Microsystems in Palo Alto, Calif. Theworkstation is connected to a local area network which providesconnection to suitable storage devices which are represented by block520.

[0047] The storage devices 520 include programs and files of thecomputer system 505 which are used in the schematic design, the netlistcreation and simulation of the circuit. The programs and files of thecomputer system include an operating system 540, a flat netlistertraversal engine 544, a flat netlist formatter 550, a “Node” list 552, a“MeasI Property” list 554 (_MS_FN_MEASI), a “Supply” list 556(_MS_FN_SUPPLIES), simulator software 560, a schematic design tool 570,the schematic 102, and the flat netlist 402.

[0048] Flat Netlister Traversal Engine

[0049]FIG. 6 is a block diagram illustrating a flat netlister traversalengine 544 which includes a conventional flat netlisting driver 545 anda flat netlist formatter 550 provided by the invention for producing theflat netlist 402 in accordance with the invention. The flat netlistingdriver 545 includes a database traversal block 610 and query functions630. The database traversal block 610 walks through the designedschematic's hierarchy of symbol instances and nets to determine theprimitive devices for each instance on the schematic 102 and convertsthe symbol instances from schematic 102 into the appropriate text stringof netlist 402. The flat netlisting driver 545 reads libraries 640 toallow the-flat netlisting driver to define the most primitive level forthe devices that comprise each instance on the schematic. The queryfunctions 630 are used in the creation of the flat netlist 402.

[0050] The flat netlist formatter 550 provides user-supplied functionsfor use by the flat netlisting driver 545 in creating flat netlists,such as flat netlist 402, with “artificial” nets in accordance with theinvention. In this example, these user-supplied functions are called bya function “NLPCompleteElementString” of the flat netlisting driver 545.The flat netlisting driver produces a name map 660 which is a datastructure which aids in post-simulation highlighting within a schematicas is known in the art. The data structure 660 associates the net namesof the artificial nets with the net names of the called out nets thatthe artificial nets replace.

[0051] The flat netlisting driver 545 and the flat netlist formatter 550comprise software programs residing in computer system 505 or any othersuitable media or computer program product which is capable of providinga computer readable program code. In one embodiment, flat netlistingdriver 545 and the user-supplied functions which comprise the flatnetlist formatter 550 can be written in SKILL code, a computer languageprovided by Cadence Design Systems, Inc., San Jose, Calif. In otherembodiments, other computer languages, such as Con, Pascal, andSmallTalk computer languages could be used as well.

[0052] Netlist Creation

[0053] The following description illustrates the implementation of theinvention in creating the flat netlist 402 from the schematic 102, FIG.2, on which an instance, such as instance GI0 of inverter 204, has theMeasI property value “inv0 vcc!”. The implementation discussed hereintherefore describe the code to generate the proper simulator-specificnetlist representation for the HSPICE simulator available from MetaSoft.Though other simulators can be supported, their netlist representationsare variations of the simulator referenced herein. The completed flatnetlist can be fed as an input to a simulator in step for simulationpurposes.

[0054] For the flat netlister, the software evaluates all hierarchicalparameters and delivers the information as if the design were flat.Thus, the properties on each instance are immediately available. Theprocess of circuit designing and netlisting is abbreviated in theflowchart of FIG. 7. FIG. 7 illustrates the processing done by the flatnetlister traversal engine 544, including the conventional flatnetlisting driver 545 (FIG. 6) and the flat netlist formatter 550,provided by the invention, in the creation of the flat netlist 402.

[0055] Referring to FIG. 7, along with FIGS. 3B, 5 and 6, at step 702,the schematic 102 is created using the schematic design tool 570 andstored in the schematic data file 102 (FIG. 5). At step 704, flatnetlisting driver 545 opens the file for schematic 102 and step 706traverses the hierarchy of the schematic 102. Step 708 locates eachinstance of each device on the schematic in sequence.

[0056] Step 710 determines whether or not the current instance is aprimitive device. If the current instance is not a primitive device, theprocedure returns to step 706 and resumes traversing of the hierarchy tolocate the next instance. When a primitive instance of a device, such asMPA (i.e., M5) of instance GI1 of “inv”, for example, is found at step710, a function “NLPCompleteElementString” of the flat netlisting driver545 passes control to the flat netlist formatter 550 for executinguser-provided functions.

[0057] At step 712, the flat netlist formatter 550 determines if thecurrent instance includes the MeasI property. If so, as in the case ofinstance MPA of “inv” GI1 which “inv” has the property “Meas1=inv1vcc!”, step 714 determines if the particulars of the property for thisinstance have been placed in the MeasI Property list 554. If not, step716 updates the list MeasI Property 554, first parsing the MeasIproperty to obtain the supply name and the net name of each of the net,or nets, identified by the property. The supply name is added to theSupply list 556 and the MeasI Property list 554 is updated to add theproperty for the current instance. In the case of the MeasI propertyassigned to instance GI1 of inverter 204, the property value is “inv1vcc!”. The net names of the artificial nets added to the MeasI Propertyfile and can be associated in a map with the net names of the called outnets for each instance. The map can be a look-up structure that is partof the MeasI Property file or a separate look-up structure.

[0058] The procedure continues to steps 718-720, where for each net ofthe current instance, the MeasI Property list 554 is read to determineif the net is listed in the MeasI Property list 554. If so, step 724causes the net to be swapped in the Node list 552 for the net calledout, so that the artificial net will be printed in place of the netcalled out. In the example, net inv1_1 is created and is substituted fornet 1 (vcc!), the net that is connected to the source of instance MPA.

[0059] The procedure returns to steps 718-720 to process the next nodebecause instance MPA has four nets. The instance MPA has a second netthat is contained in the MeasI Property list 554, namely, the net bywhich substrate bias is applied to instance MPA. Accordingly,“artificial” net inv1_1 is swapped for this net in the Node list 552.The other two nets of instance GI1, namely net 10 (I1/net6) and net5(A), are not contained in the MeasI Prop list 554, and so these netsare not modified and are added to the netlist file unchanged. See, forexample, line 4.37 of the flat netlist 402 of FIGS. 4A and 4B, in whichinv1_1 has been substituted for both of the occurrences of “net 1”(vcc!) in the instance GI1 of the “inv”, but net numbers 10 and 5 areprinted in the netlist When all four nets of the instance MPA have beenprocessed, from step 720, the process flows to step 726 which prints thenodes and the device parameters of the current instance to the netlistfile. Step 726 then returns control to the flat netlisting driver tolocate the next instance. A similar procedure is followed for instanceof device MNA of instance GI1 of “inv”. However, none of the four netsof device MNA of instance GI1 is listed in the MeasI Property list 554and so the four nets are added to the netlist file unchanged. See, forexample, line 4.31 of the flat netlist 402 of FIGS. 4A and 4B.

[0060] A similar procedure is followed for the instances of primitivedevices MPA and MNA of instance GI0 of “inv” to create the artificialnet inv0_1 and swap this net for the net 1 (vcc!) the netlist See forexample, line 4.48 for instance MPA (and line 4.42 for instance MNA) Anexample of a segment of code for the procedure for creating artificialnets and substituting the artificial nets for the nets included in theMeasI property is shown in FIG. 8A, lines 2-37.

[0061] If step 712 determines that the current instance does not havethe MeasI property, such as in the case of the four primitive devicesMPB, MPA, MNB and MNA of the instance GNA0 of NAND gate, the nets arenot modified. Thus, for the instance of GNA0 of NAND gate, step 726prints the nets (unmodified) and the devices of the this instance to thenetlist file 402. See, for example, lines 4.55, 4.57, 4.59 and 4.61 ofthe flat netlist 402 of FIGS. 4A and 4B, which describe the nets forfour transistors of the instance GNA0 of the NAND gate, which do nothave the MeasI property.

[0062] After all instances have been processed, from step 708, theprocedure continues to step 728 to execute a further procedure“MSfnlFooter” of the formatter 550 to print the information contained inthe Supply list 556 to the netlist file. In the example, a supply“vinv0_1” is declared for instance GI0 of “inv” as being connectedbetween “artificial” net inv0_1 and net 1 (vcc!), with the supplyproviding zero volts, as is represented by the four terms listed in line4.64 of the netlist 402 (FIG. 4B). Similarly, line 4.65 declares asupply “vinv0_1” for instance GI1 of “inv”, the supply being connectedbetween “artificial” net inv1_1 and net 1 (vcc!), with the supplyproviding zero volts, as is represented by the four terms listed in line4.65 of the netlist 402 (FIG. 4B). An example of a segment of code forthe procedure for adding the information contained in the Supply list556 to the netlist file is shown in FIG. 8B, lines 39-53. When thesupply information has been added to the netlist file, the procedure isdone.

[0063] In the exemplary embodiment, different property names wereapplied to the two instances GI0 and GI1 of “inv” and uniquelyidentified “artificial” nets were created for each of the instances.However, it is possible to apply the same property name to differentinstances, and/or to instances at different levels of hierarchy.Applying the same property name to both instances of “inv” results inthe current through both instances of“inv” to be added together duringsimulation. Stated in another way, the supply is merged to a combinationof nets which can be nets in the same instance or in differentinstances. Moreover, the property can be assigned to instances at alevel of the hierarchy above the level at which the instances aredefined.

[0064] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

I claim:
 1. A method for manipulating a netlist file at the time thenetlist file is being created from a data file that includes datarepresenting a circuit design schematic including a plurality ofinstances and a plurality of nets, to permit measurement of current flowthrough at least a first net of one of said instances during asubsequent simulation process, said method comprising: assigning aproperty to said one instance, the property identifying said first netthrough which current flow is to be measured and a supply to beconnected to the identified net; creating the netlist file by traversingthe hierarchy of the schematic to locate each of said instances insequence; checking each instance located to determine if the instancelocated has the property; creating a uniquely identified artificial netfor said first net that is identified by the property; and substitutingthe artificial net of said one instance for the identified net of saidone instance in the netlist file at the time that the netlist file isbeing created.
 2. The method according to claim 1 , including extractingfrom the property the identity of a supply to be connected between theartificial net and the identified net of said one instance, anddeclaring the supply as being connected between the artificial net andthe identified net.
 3. The method according to claim 1 , wherein one ofsaid instances includes a second net through which current flow is to bemeasured, said one instance having a property assigned thereto foridentifying the second net and a supply to be connected to the secondidentified net of said one instance; and including creating a seconduniquely identified artificial net, and substituting the secondartificial net for the second identified net at the time that thenetlist file is being created.
 4. The method according to claim 3 ,including associating in a data structure the net names of saidartificial nets with the net names of said associated identified netsfor each instance.
 5. The method according to claim 4 , whereinassociating said artificial net for said one original net comprises thesteps of extracting a net name from the property; creating an artificialnet number for the extracted net name; and substituting the artificialnet number created for the identified net number in the netlist file. 6.The method according to claim 3 , wherein said first and second nets arenets of the same instance.
 7. The method according to claim 3 , whereinsaid first and second nets are nets of first and second instances, andincluding assigning the same property to said first and secondinstances.
 8. The method according to claim 1 , wherein the designschematic includes a plurality of levels of hierarchy, and wherein theartificial net is global to all of the levels of the hierarchy of thedesign schematic.
 9. A system for manipulating a netlist file at thetime the netlist file is being created from a data file that includesdata representing a circuit design schematic including a plurality ofinstances and a plurality of nets, to permit measurement of current flowthrough at least a first net of one of said instances during asubsequent simulation process, said system comprising: an inputmechanism for assigning a property to said one instance, the propertyidentifying said first net through which current flow is to be measuredand a supply to be connected to the identified net; a traversal enginefor creating the netlist file, wherein the traversal engine performs thesteps of: traversing the hierarchy of the schematic to locate each ofsaid instances in sequence; checking each instance located to determineif the instance located has the property; evaluating the property for atleast said one instance, creating a uniquely identified artificial netfor said first net that is identified by the property; and substitutingthe artificial net for the identified net of said one instance at thetime that the netlist file is being created.
 10. The system according toclaim 9 , wherein the traversal engine performs the additional steps ofextracting from the property the identity of a supply to be connectedbetween the artificial net and the identified net of said one instance,and declaring the supply connected between the artificial net and theidentified net.
 11. The system according to claim 9 , wherein one ofsaid instances includes a second net through which current flow is to bemeasured, said one instance having the property assigned thereto foridentifying the second net and a supply to be connected to theidentified second net; and wherein the traversal engine performs theadditional steps of: creating a second uniquely identified artificialnet, and substituting the second artificial net for the secondidentified net at the time that the netlist file is being created. 12.The system according to claim 11 , including a data structureassociating the net names of said artificial nets with the net names ofsaid associated identified nets for each instance.
 13. The systemaccording to claim 12 , wherein the traversal engine performs theadditional steps of: extracting a net name from the property; creatingan artificial net number for the extracted net name; and substitutingthe artificial net number created for the identified net number in thenetlist file.
 14. The system according to claim 11 , wherein said firstand second nets are nets of the same instance.
 15. The system accordingto claim 11 , wherein said first and second nets are nets of first andsecond instances, and wherein said traversal engine performs theadditional step of assigning the same property to said first and secondinstances.
 16. The system according to claim 9 , wherein the designschematic includes a plurality of levels of hierarchy, and wherein theartificial net is global to all of the levels of the hierarchy of thedesign schematic.
 17. A computer program product comprising a computerusable medium having a computer readable program code means embodiedtherein for causing a netlist file to be manipulated at the time thatthe netlist file is being created from a data file that includes datarepresenting a circuit design schematic including a plurality ofinstances and a plurality of nets, to permit measurement of current flowthrough at least a first net of one of said instances during asubsequent simulation process, said computer program product comprising:computer readable program code means for assigning a property to saidone instance, the property identifying said first net through whichcurrent flow is to be measured and a supply to be connected to theidentified net; computer readable program code means for creating thenetlist file by traversing the hierarchy of the schematic to locate eachof said instances in sequence; computer readable program code means forchecking each instance located to determine if the instance located hasthe property; computer readable program code means for creating auniquely identified artificial net for said first net that is identifiedby the property; and computer readable program code means forsubstituting the artificial net for the identified net of said oneinstance in the netlist file at the time that the netlist file is beingcreated.
 18. The computer program product according to claim 17 ,including computer readable program code means for extracting from theproperty the identity of a supply to be connected between the artificialnet and the identified net of said one instance, and computer readableprogram code means for declaring the supply as being connected betweenthe artificial net and the identified net.
 19. The computer programproduct according to claim 17 , wherein one of said instances includes asecond net through which current flow is to be measured, said oneinstance having the property assigned thereto for identifying the secondnet and a supply to be connected to the second identified net; andincluding computer readable program code means for creating a seconduniquely identified artificial net, and computer readable program codemeans for substituting the second artificial net for the secondidentified net at the time that the netlist file is being created. 20.The computer program product according to claim 19 , including computerreadable program code means for associating in a data structure the netnames of said artificial nets with the net names of said associatedidentified nets for each instance.
 21. The computer program productaccording to claim 20 , including computer readable program code meansfor extracting a net name from the property, computer readable programcode means for creating an artificial net number for the extracted netname; and computer readable program code means for substituting theartificial net number created for the identified net number in thenetlist file.
 22. The computer program product according to claim 19 ,wherein said first and second nets are nets of first and secondinstances, and including computer readable program code means forassigning the same property to said first and second instances.